MC-6809^™ Trunked Central Controller

Trunked System Controller

Single-Site, Simulcast, and AMSS 6809 trunked system controllers have similar hardware components. In this module, I will only be describing the MC-6809 SMARTNET II Single-Site trunked controllers...

Functional Blocks:

These controllers are structured around three interface subsystems:

• Transmitter Interface Board (TIB)
• Receiver Interface Board (RIB)
• Inbound Recovery Board (IRB)

And three microprocessor subsystems (called Site Controller Boards, SCBs):

• Central Site Controller (CSC)
• Transmitter Site Controller (TSC)
• Receiver Site Controller (RSC)

Other Site Controller Boards are: (not shown)

• Simulcast Data Concentrator Board (DCB)
• Simulcast Remote Site Controller (RSC)
• AMSS Data Concentrator Board (ADCB)
• AMSS Site Audio Board (SAB)

In addition, controller board configurations exist for the Master Controller Board (MCB) and the Trunked Console Interface (TCI).

Transmitter Interface Board (TIB)

Functions:

The Transmitter Interface Board (TIB) receives the microprocessor address and data bus signals from the Transmitter Site Controller (TSC) and converts them into data and control signals that are used by the Trunked Radio System base repeater transmitters. The signals sent to the repeaters include:

• TDATA: OSW, HSHS (Type-I only), LSHS, and Disconnect Tone
• PTT: Transmitter keying
• Mute with Tickle, In Cabinet Repeat/Failsoft Timer Control (slow failsoft)

The signal received from a repeater station (TSTAT) incorporates the following information:

• Micor: Forward Power, Reflected Power, Keyed A+
• MSF5000 and Quantar/Quantro: Forward Power, Reflected Power, Transmitter Activity, Synthesizer Lock, TDATA Detect

Each TIB can control up to 7 transmitters, therefore three TIB modules are required for a 20 channel system.

Controls:

Channel 1-7 Pushbuttons Used to manually disable (depressed) or enable (released) channel operation. Must be activated by TSC keylock Run/Service Enable switch. Proper activation requires the following procedure:

• Step 1. Turn TSC key switch to Service Enable position.
• Step 2. Select (cycle as required) enable or disable position of channel pushbutton(s)
• Step 3. Turn TSC key switch to Run position.

Indicators:

• Transmit LEDs: Light when channel(s) repeater PTT signal active.
• Disabled LED: Lights when channel(s):
  • Manually disabled by CHANNEL 1-7 pushbutton(s), or
  • Fail transmitter status check via TSC software diagnostic test; or corresponding base-repeater provides a non-active TSTAT signal from its Trunked Control board.
  • Software disable by SMT command.

Functional Block Diagram:

• Buffer: Provides support for I/O (Input/Output) data transfer to/from TSC
• Address Decoder: Provides support for routing data to/from PIAs
• PIA#1: Performs the following functions:
  • Controls the front panel disabled LED
  • Converts switch input (disable switch) and/or interprets TSTAT input through 2:1 MUX (Multiplexer) circuit
• PIA#2: Performs the following functions:
  • Interprets data input from TSC to set condition of latches that generate appropriate control signals (PTT, MUTE, H/L)
  • Takes TDATA from TSC and directs it to correct P-S converter where the counter clocks it out at the required baud rate.
• S8 Fake: Used in AMSS/Simulcast Systems where there is not an equal number of channels at all remote sites. It fakes active TSTAT.
• S9: Removes PTT output in Fake operation.
• A/B Jumpers: Support simulcast operation, i.e. all data uses high speed path and Hi/Low input now controls mute output.

Refer to Transmitter Interface Board Manual (68P81084E51) for detailed description of the TIB operation.

Receiver Interface Board (RIB)

The Receiver Interface Board (RIB) provides the interface between the Trunked base repeater receiver and the MC6809 Microprocessor used in the Receiver Site Controller (RSC). Since each RIB interfaces with up to seven receivers, four RIB modules are required for a system employing 28 channels. Each RIB is used to:

• Detect the inbound 1800 Hz acknowledge tone from mobile units requesting a voice channel (Type-I)
• Detect the inbound 105.8 Hz (default) connect tone from mobile units transmitting on a voice channel
• Detect the inbound 163.6 Hz disconnect tone from mobile units dekeying on the assigned voice channels
• Receive the RF carrier status (RSTAT) from the repeater, indicating that the repeater receiver is quieted
• Interface to the M6800 Microprocessor via two MC6809 Peripheral Interface Adapters (PIAs)

Controls:

Channel 1-7 Pushbuttons: Used to manually disable (depressed) or enable (released) channel operation. Must be activated by RSC keylock Run/Service Enable switch. Proper activation requires the following procedure:

• Step 1. Turn RSC key switch to Service Enable position
• Step 2. Select (cycle as required) enable or disable position of channel pushbutton(s)
• Step 3. Turn RSC key switch to Run position

Indicators:

• Rcv LEDs: Lights when RSTAT signal from corresponding base-repeater(s) is active (seven per RIB). Note: Active RSTAT signal results when base repeater squelch circuitry determines, from ac coupled receiver discriminator signal, whether or not channel is sufficiently quieted to indicate carrier is present.
• Disabled LEDs: Lights when channel(s):
  •  a) Manually disabled by Channel 1-7 pushbutton(s), or
  •  b) Fail tone detector check via RSC software diagnostic test, or exceed assigned carrier malfunction time-out period (factory defaulted to 50 consecutive seconds). Note: Carrier malfunction parameter is adjustable (1-253 seconds) through use of PARM command by system manager. Setting of 254 disables this timeout.
  •  c) Software disabled by SMT command.

Functional Block Diagram:

• Data Buffer: Data I/O interface to RSC microprocessor.
• Address Buffer: Address data input interface to RSC microprocessor.
• PIA#1 (Peripheral Interface Adapter #1): Under control of RSC microprocessor performs the following functions:
  • Lights amber disables LED.
  • Reports switch position change of enable/disable switch.
  • Drives test tone decoder to support software diagnostics testing.
• PIA#2 (Peripheral Interface Adapter #2): Under control of RSC microprocessor performs the following functions:
  • Collects tone status information from the 7 receive channel inputs.
  • Monitors active RSTAT input from the 7 receive channel inputs.
• Multlplexers: Combine inputs from multiple channels to input into PIAs.
• Logic Buffers: Provide input interface for timing signals and for audio from base repeater stations.
• Voltage Limiters: Remove possible noise sources for quicker tone detection.
• Filter: 300 Hz Low Pass filter to remove radio operator generated audio to provide quicker and easier connect tone detection.
• Buffer: Provide input interface for RSTAT signal, which also directly activates the front panel LED.

Refer to Transmitter Interface Board Manual (68P81040E11) for detailed description of the RIB operation.

Inbound Recovery Board (IRB)

The Inbound Recovery Board (IRB) interfaces with four Motorola Trunked Radio System Base Repeaters (control channels) and serves to decode data from one of the four. It contains three signal-processing subsystems: a high speed analog-to-digital converter, bit synchronism recovery circuitry, and memory buffers.

The IRB, in conjunction with the Receiver Site Controller (RSC), processes the 78-bit Inbound Signal Word (ISW). The ISW data arrives at the IRB in synchronization with the timing format known as the Word Frame Interrupt (WFI).

Note that the propagation delay can cause a 1 to 3-bit uncertainty in the arrival time of the 78-bit ISW data! The RSC software enables the IRB to compensate for this uncertainty.

The RSC software also controls the base station's generation of the CCI (Control Channel Indicate) signal for the current control channel selection, directing the received audio through the correct path in the TCM and providing the correct offset and amplification for all incoming data.

Indicators:

• Control Chan 14 LEDs: Lit (one at a time) to indicate which channel is presently assigned as the control channel.
• Decode LED: Flashes to indicate decoding of valid Inbound Signaling Word (ISW).
• Un-Squelch LED: Lit when synchronous squelch circuit determines a valid ISW may have been received.
• Failure LED: Lit when board fails.

Functional Block Diagram:

• Input Analog MUX: Allows audio input from currently designated control channel base station (controlled by RSC through PIA).
• Squelch Circuit: Interprets input to determine if valid ISW may be present during a WFI
• Bit Sync: Used to provide input for bit centering for optimum data decoding.
• Audio MUX: Provides bit slicing of audio input and directs squelch and bit sync inputs to A/D Converter for value interpretation.
• A/D Converter: Converts input audio slices and other analog inputs that require interpretation to digital data.
• Data MUX: Directs converted digital data to memory buffers or RSC microprocessor for further processing.
• Memory Buffers: Store sliced and converted ISW input temporarily until further processing requires retrieval of this data.
• Address MUX: Controls input to/from memory buffers.
• Address Counters: Support address MUX in data storage and retrieval.
• Counter: Adjustable time delay to control start time of ISW processing to support system RF designed coverage.
• Control Channel Selector: Generates CCI for currently selected control channel base station.
• PIA: Lights LED's and provides control interface for RSC microprocessor.

Refer to Transmitter Interface Board Manual (68P81040E09) for detailed description of the IRB operation.

Central Site Controller (CSC)

The CSC board consists of a microprocessor unit with enough support circuitry to interface with the RSC, TSC, and the System Manager Terminal (SMT). The CSC communicates with the RSC, TSC, and SMT via dedicated RS-232-c interfaces. The CSC hardware is similar to the other site controllers. The CSC distinguishing characteristics result from the unique software package, which is programmed into EPROM memory on the board. The CSC module accepts inputs from the RSC, decides upon the appropriate course of action, and tells the TSC what to do. The major functions of the CSC include:

• call processing
• call queuing
• resource allocation
• diagnostics
• site-to-site protocol and
• logging of usage statistics
• SAC database

The CSC has provisions for interfacing with a keyboard terminal. The System Manager Terminal (SMT) Interface provides the ability to modify system parameters and databases and interrogates current system status.

Transmitter Site Controller (TSC)

The TSC board consists of a microprocessor unit with enough support circuitry to interface with the Transmitter Interface Board (TIB) and the CSC. The TSC communicates with the TIB via the address and data bus structure on the backplane interconnect board. The TSC communicates with the CSC via a dedicated RS-232-c interface. The TSC hardware is similar to the RSC/CSC hardware. However, the TSC software package (contained in EPROM memory) is entirely different.

The major functions programmed into the TSC software package include:

• Generation of outbound data from the system control channel
• Generation of subaudible data (which is superimposed on all voice channel communications)
• Base repeater station control
• RF power monitoring
• Generation of repeater station identification as required by the FCC
• Maintenance of communication protocol between other boards and peripheral devices

The TSC is the source for all intersite clock signals.

Receiver Site Controller (RSC)

The RSC board consists of a microprocessor unit with enough support circuitry to interface with the Inbound Recovery Board (IRB). the Receiver Interface Board(s) (RIBs), and the Central Site Controller (CSC) board. The control functions are found in the software (EPROM memory) associated with this board, The RSC communicates with the IRB and RIB via address and data bus structure on the backplane interconnect board. The RSC communicates with the CSC board via a dedicated RS-232-c interface.

The major functions programmed into the RSC software package are

• Inbound word (ISW) recovery
• Voice channel monitoring
• Communications protocol with the CSC

Indicators:

• Run LED: Lights when board is functioning normally
• Disable LED: lights when board is disabled
• Test Active LED: Lights while software diagnostic test is running
• Test Failure LED: Lights when a software diagnostic test fails, and normal operation may be disabled

Controls:

• Disable Pushbutton: Function is dependent on SCB application and software version
• Reset Pushbutton:
  • When depressed, it resets system hardware, re-initializes system variables, and performs system software diagnostics test:
    •  a) Test of RAM
    •  b) Check sum test
    •  c) Resets TSC and RSC
  • When depressed, it resets TSC hardware and performs TSC software diagnostic test. The TSC software diagnostic test includes:
    •  a) Test of each RAM integrated circuit
    •  b) Checksum test of the EPROM integrated circuit, TIB check (keys channel and checks transmitter status)
  • When depressed, it resets RSC hardware and performs RSC software diagnostic test. The software diagnostic test includes: (Note: Reset of TSC/RSC will not reset CSC.)
    •  a) test of each RAM integrated circuit
    •  b) checksum test of the EPROM integrated circuit
    •  c) IRB check (SRAM and All) converter) and
    •  d) RIB check (tone detectors)
• Test Pushbutton: On CSC it performs the same function as RESET switch but does not interrupt ongoing call traffic
• Indicator Test Pushbutton: When depressed, it lights all LEDs on all card cage boards, to allow visual LED check
• Alarm Cutoff Pushbutton: When depressed, it disables the major and minor alarm outputs. LED indicator lights when Alarm Cutoff pushbutton is depressed.
• Keylock Run/Service Enable Switch: Used to activate Reset, Disable, and Test pushbuttons. If service enable switch is normally left in the RUN position, activation of Disable, Reset, and Test switches requires the following procedure:
  • Step 1. Turn key switch to Service Enable position.
  • Step 2. Depress and release appropriate pushbutton (Disable switch will latch).

Major Functional Blocks:

A Site Controller Boards (SCB) contains a Motorola MC6809 Microprocessor complete with volatile, battery backed dynamic and static RAM, and non-volatile EPROM memory. The microprocessor unit handles 16 address and 8 data lines.

Each board contains three Asynchronous Communication Interface Adapters (ACIA's). The function of ACIA's is to provide RS-232-c serial data links to other microprocessors on other SCB's or external computers/terminals. In a CSC application the ACIA's support the following functionality:

• ACIA1: Communication with a user terminal System Manager's Terminal, (SMT) or another SCB such as the MCB for CIT operation.
• ACIA2: Communication with the RSC from the CSC
• ACIA3: Communication with the TSC from the CSC

Operation: (ACIA, Parity Checker)

• Parity Checker: The SCB employs a parity bit associated with each word which is used to detect when an error has occurred in reading the dynamic RAM.
• ACIA Baud Rate: The baud rate at which ACIA's transmit and receive data is jumper-selectable from a selection of rates generated by the baud generator. The 1.8432 Mhz crystal Y1 input is divided down to produce outputs that are 16 times the desired baud rates; divisors range between 12 for 9600 baud and 1,536 for 75 baud. A selected baud rate is buffered for the ACIAs.

  

• Interrupt Service Requests: The MPU has three interrupt service request inputs:
  • NMI: The Non-Maskable Interrupt, NMI has the highest priority. NMI is generated whenever an error is detected in the parity checking circuitry.
  • FIRQ: The Fast Interrupt Request, FIRQ, is generated whenever one of the ACIAs needs servicing.
  • IRQ: The Interrupt Request, IRQ signal, bas the lowest priority of the three interrupts and is generated by the PIA when it needs servicing.

Site Controller Modules (SCM)

Operation (Reset, Power Fail Detect, Alarms, Switches, Displays)

• Reset: Reset can be internally or externally generated for the microprocessor and the PIA. Operating the front panel reset pushbutton can generate a hardware reset. A power failure reset is an example of a internally initiated reset.
• Power Fail Detect: The Power Fail Detect circuitry uses a zener reference voltage to detect power failure. The PFD signal holds the microprocessor in the reset state while the +5 volt supply is below specification.
• Hardware Reset 'Tickle': The watchdog timer, or "tickle" circuit, insures that the microprocessor does not remain in a software error condition. Failure of the microprocessor to properly "tickle" the watchdog timer causes microprocessor reset. If the microprocessor does not generate the tickle pulse within the 150 millisecond time-out period, a reset pulse is generated which goes to the microprocessor and the PIA. The Run indicator turns off, the major alarm is set and the site Failure indicator is turned on. The initial tickle pulse is provided by the Power Failure Detect circuit.
• Major and Minor Alarm: Two D-flip-flops, one for the major and one for the minor alarm conditions are used as latches to keep the status of the major and minor alarms. In case a major or a minor alarm, the PIA sets the appropriate D-flip-flop. The major and minor alarm signals are output by dry-contact relays in the site backplane. The relay control signals are high during normal operating conditions, and low during at alarm condition. If an alarm condition occurs, an active low signal is sent to the alarm relays. Note that if the Alarm Cutoff button is depressed, the active low signal is not sent to the relays. The relays can be tested by depressing the Indicator Test push-button on the front panel. The Alarm Cutoff button cannot be depressed while testing the alarm relays. After an alarm condition occurs, the alarm may be deactivated by depressing the Alarm Cutoff switch (the alarm cutoff LED will turn on). This stops all alarm indications but does not reset the major and minor alarm D-flip-flops. These flip-flops may be reset by a return-to-power condition or by turning the Service Enable key switch from Run to the service enable position or by initiating a reset or test of the SCB.

System Frequency and Timing:

A 15.840 Mhz temperature-compensated crystal oscillator is the Master Oscillator for the board and the source of all intrasite clocks. A counter provides a divide-by-2 (7.9200 Mhz) and divide-by-4 (3.9600 Mhz) out put that is jumper selectable (JU19) for input to the EXTAL input of the MPU. The input EXTAL is the external clock source for the microprocessor. The 7.9200 Mhz output is used for fast Site Controller Board applications; the 3.9600 Mhz output is used for all other applications. Another counter provides a divide-by-5 (3.168 Mhz) output for input into the Clock Generator circuit.

The MPU divides the EXTAL input by four to generate processor clocks. Refer to the manual for detailed description.

The 3.168 Mhz clock is supplied to a divide-by-11 counter to generate a 288 kHz clock for external use. The 288 kHz signal is also fed into a divide-by-16 counter, then into a divide-by-5 counter, to generate a 3600 Hz clock. The 3600 Hz signal is divided by 6 to provide a 600 Hz signal. The 600 Hz signal is further divided by 15 to produce 40Hz clock. 40 Hz is divided by two to provide 20 Hz clock used in the watchdog timer circuitry. 40 Hz is also routed to the PIA as an interrupt driven timing signal. The 600 Hz clock is also input to a divide-by-14 counter, to produce WFI (42.86 Hz Word Frame Interrupt).

Intersite Clocks: Coordination of ISW-OSW timing requires synchronization of the 3600 Hz, 600 Hz, and WFI clocks between sites. Only one SCB, designated as the Transmit Site Controller, generates intersite clocks for all boards on the common bus. When jumper JU2 is removed from the TSC, the clock signals are then connected to the common bus and to the PIA on the clock source SCB. When jumper JU2 is inserted, the RSC and CSC are designed as intersite clock receivers. This isolates the CSC/RSC PIA from its on-board clock source.